An integrated circuit contains various semiconductor devices and a plurality of conducting metal paths that provide electrical power to the semiconductor devices and allow these semiconductor devices to share and exchange information. Within the integrated circuit, metal layers are stacked on top of one another using intermetal or interlayer dielectric layers that insulate the metal layers from each other.
Normally, each metal layer must form an electrical contact to at least one additional metal layer. Such electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers, and filling the resulting via with a metal to create an interconnect. Metal layers typically occupy etched pathways in the interlayer dielectric. A “via” normally refers to any feature such as a hole, line or other similar feature formed within a dielectric layer that provides an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer. Metal layers connecting two or more vias on the same dielectric layer are normally referred to as trenches.
The use of copper (Cu) metal in multilayer metallization schemes for manufacturing integrated circuits creates problems due to high mobility of Cu atoms in dielectrics, such as SiO2, and Cu atoms may create electrical defects in Si. Thus, Cu metal layers, Cu filled trenches, and Cu filled vias are normally encapsulated with a barrier material to prevent Cu atoms from diffusing into the dielectrics and substrate material, such as Si. Barrier layers are normally deposited on the sidewalls and bottom of a trench or via prior to Cu seed deposition, and may include materials that are preferably non-reactive and immiscible in Cu, provide good adhesion to the dielectrics and can offer low electrical resistivity.
An increase in device performance is normally accompanied by a decrease in device area or an increase in device density. An increase in device density requires a decrease in via and trench dimensions resulting in larger aspect ratio (i.e., depth to width ratio) metallization features. As metallization feature dimensions decrease, and aspect ratios increase, it becomes increasingly more challenging to form diffusion barrier layers with adequate thickness on the sidewalls and/or bottom of such features. In addition, as via and trench dimensions decrease and the thicknesses of the layers in the vias and trenches decrease, the material properties of the layers and the layer interfaces become increasingly more important. In particular, the present inventors have recognized that impurity levels of metallization features that may have been previously acceptable can cause manufacturing yield and/or device reliability problems as device scaling continues.